Cart
0
- The requirements of the AI era demand integrated core chips, driving vertical integration
- Chip makers are just now beginning limited production of 3D packaging
New developments in semiconductor packaging are contributing to the quest to extend Moore’s Law, the predictive model of adding more transistors to a semiconductor. One promising development is advanced packaging, which can better manage the power consumption of a collection of chips while shrinking their total size.
Protective Wrap
The classic definition of semiconductor packaging is a container that houses and protects exceedingly small wires within a semiconductor and allows it to connect to other components, such as power within an electronic device. Think of packaging as the protective wrap that prevents damage to the semiconductor while the chip is being handled and used.
Advanced packaging takes this concept even further. The key difference with advanced packaging is its ability to bring chips with multiple functions together to form a system.
- For example, advanced packaging might join logic chips, central processing units (CPU), graphical processing units (GPU), radio frequency (RF) chips, and memory onto a single chip. Such an ecosystem of complex functions operates at much faster speeds than they would separately.
The advanced requirements of artificial intelligence (AI) require integrated multi-core chips, which provide greater capabilities than stand-alone semiconductors can provide.
A primary goal of the semiconductor industry is to improve manufacturing variables known as PPAC: performance, power consumption, area (size of the semiconductor), and cost. To decrease the overall area of a chip, while simultaneously boosting performance and lowering both power consumption and cost, various components are brought together as a system into one advanced packaging environment.
3D Challenges
As of now, the most common method of advanced packaging is called 2.5D, so titled because it is not fully three-dimensional (3D). In 2.5D packaging, multiple semiconductor devices are connected linearly on a shared base instead of stacked upward as true 3D packaging would require. Of course, the system’s footprint, which stacks chips vertically, as opposed to horizontally, would be much smaller. As one example, a smaller form factor is obviously a great benefit for mobile phones.
One of the greatest challenges in achieving full 3D packaging is joining multiple layers together. To achieve this, it is critical to apply an insulating film to the structure to prevent the electrical current from leaking.
- The process of applying insulating film tightly around the semiconductor is called dielectric deposition.
- Deposition methods are divided into the following two categories: (1) physical vapor deposition (PVD) and (2) chemical vapor deposition (CVD).
As advanced semiconductors continue to shrink, many critical process steps rely on the deposition of exceptionally high-quality dielectrics (smooth, void-free films that meet exacting thickness, feature coverage, mechanical stress, and electrical requirements).
Process Pioneer
Lam is a pioneer in deposition equipment and processes. To address diverse and challenging requirements, Lam’s deposition equipment must provide flexibility for a wide range of process applications, while maintaining high productivity and low cost.
- Lam’s VECTOR® products use one process called plasma-enhanced chemical vapor deposition (PECVD). PECVD deposition helps enable hybrid bonding, a key component for 3D advanced packaging.
For example, Lam Research is one of the first to deposit a proprietary layer of protective film on the back side of wafers with its VECTOR® DT product, which eliminates warping that can occur in wafers because of bonding components together.
On the other end of the spectrum, etch products remove debris (unwanted masks, residues, and films) from a semiconductor. When you stack multiple layers, for example, an edge is formed. Lam’s Coronus® bevel etch products remove any imperfections along the edge caused by 3D packaging.
Global Collaboration
Lam’s strong position in the semiconductor industry and our global collaborations allows our continued leadership in advanced packaging development.
Since advanced packaging is still new to the industry, our development starts with the fundamentals. We consider what is really needed. For example, are our film development processes resilient enough to meet our customers’ requirements?
Then we collaborate directly with our logic and memory customers to speed time to market. Finally, we form relationships to work globally with university professors and research institutions on advanced packaging.
New Era
The semiconductor industry is moving 3D advanced packaging concepts into production. For example, Taiwan Semiconductor Manufacturing Company (TSMC) has begun limited production of 3D advanced packaging, and the movement toward high-volume manufacturing is not far off.
Ensuring advanced packaging is commercially successful is part of Lam’s mission to drive semiconductor breakthroughs that define the next generation. We are bringing together all of Lam’s research labs, innovative thinking, and our best-of-breed equipment – everything – to become even more innovative to deliver solutions for this important new packaging area.
Ming Li is VP, Strategic Products, PECVD Engineering
