Metal-Oxide-Metal Capacitor Simulation and Modeling by Virtual Fabrica

Metal-Oxide-Metal (MOM) capacitors are passive radio frequency (RF) capacitive devices that are a common component in semiconductor logic chips [1]. A SPICE model of a MOM capacitor is typically used by designers during the design and performance evaluation of logic chip RF circuitry. Traditionally, it may take at least 3 months from the completion of the design layout, wafer fabrication, final electrical testing and model fitting. This silicon-based development process is long and costly, and virtual experimentation can be a faster and less costly alternative. In this study we will simulate and model a MOM device using SEMulator3D^® virtual process modeling.

A MOM device has three major components: a bottom shielding plate (BP), and 2 finger nets (Finger Net 1 and Finger Net 2 (Fig. 1 (d))). The major portion of the capacitance is located between Finger Nets 1 and 2, while the bottom shielding plate is used to avoid interference between the MOM capacitors and the FEOL transistors in the logic chip.

The capacitance between the Finger Nets is calculated as a function of the distance, overlap area and material dielectric constant between the two Finger Nets. Thus, to ensure that the capacitance extraction results are accurate during simulation, the ILD film stacks (material thickness, dielectric constant) and metal line profiles (CD, SWA, thickness) must be accurately represented in the simulation model. The film stack and metal profiles can be calibrated in the model using silicon test data, to ensure that the virtual MOM structure accurately reflects the behavior of an actual silicon device.

*Figure 1: (a) MOM layout, (b) top view, (c) 3D view and (d) the nets definition of the virtual MOM device*

To systematically investigate the MOM capacitors, a virtual experiment was executed using different values for the number of fingers (NF), number of metal layers (NL) and the metal-to-metal spacing (S), in order to calculate the expected capacitance performance. Figure 2 displays multiple 3D virtual structures with 4 different values for NF, NL and S. Using these virtual structure, the resulting simulated capacitance between Finger Nets 1 and 2 can be extracted.

*Figure 2: 3D structure with the 4 typical split conditions on NF, NL and S.*

We used 2 methods to model and predict the Net 1 to Net 2 capacitance: a compact model and a neural network model [5]. Figure 3 displays the fitting results using the compact model. The fitting results are not perfect since the film stacks and metal profiles (thickness and SWA) vary at different layers. To overcome this problem, a neural network model containing one hidden layer, and 6 hidden nodes was subsequently used to fit the data. During this fitting process, 70% of the data was used in the training set for the neural net, while the rest of the data (30%) was used in the test set to avoid overfitting issues. Figure 4 displays the fitting results using a neural network approach. Figure 5 displays a comparison between the compact model and the neural network model. A maximum and mean error of 9.8×10^-3 and 1.3×10^-3 pF were obtained using the compact model, while they were only 1.0×10^-3 and 2.0×10^-4 pF using the neural network model. The average relative error of the neural network model was only 0.81% while the compact model had an average relative error of 3.7%, showing that the neural network model is superior for MOM device modeling.

Figure 3: *Predicted C vs Actual C in compact model*

*Figure 4: Predicted C vs Actual C in NN model.*

In this study, a MOM device was fabricated and calibrated in a virtual fabrication platform. A full factorial experiment varying the number of layers (NL), number of fingers (NF) and metal spacing (S) was executed to evaluate capacitance performance. A compact MOM model and a neural network model were fitted from the simulation data for use in a SPICE model. The neural network model had a 0.81% fitting error from the fitted data, which was substantially lower than the fitting error obtained using the compact model. In this case, virtual experimentation allowed us to model the capacitance behavior of a MOM device with different numbers of fingers, metal layers and metal-to-metal spacing (S), without the use of lengthy, expensive silicon-based testing.

QingPeng Wang is a senior semiconductor process and integration engineer, Semiverse Solutions

Reference

1. Kim, et al., IEEE Electron Device Letters, vol. 28, no. 7, pp. 616-618. July 2007